Many powerful new features of computer systems require the addition of bus agents which compete for access to a shared bus. As bus utilization increases, management of traffic on this shared bus becomes increasingly important. If unsophisticated methods of bus arbitration govern the bus, large bus access latencies may result, thereby increasing the risk of bus agent starvation.
In order to compensate for latencies which may be experienced in attempting to access a shared bus, various bus agents often include buffers providing temporary storage. Such buffering can reduce the risk of a bus agent starving, or becoming unable to continue normal operation due to lack of access to the bus. In one case, these buffers allow the bus agent to accumulate data from an external input while waiting to write to another device on the bus. Other buffers may be used to store incoming data retrieved from the bus prior to the time at which it is required.
Multiple element data transfers requiring buffering (data streams) may thus originate from external inputs or from bus transactions. In either arrangement, a buffer may be exhausted if access to the shared bus is not granted in time. In the former case, if the entire buffer fills and is no longer able to accommodate additional data, this buffer is exhausted, and additional data causes buffer over-run. In the latter case, if the entire buffer empties and there is no reserve data for the bus agent, this buffer is also exhausted and additional requests for data cause buffer under-run.
When the buffers of a bus agent are exhausted, either data is lost or operational latencies increase. While some bus agents are able to accommodate temporary buffer exhaustion, even these agents experience an unacceptable degradation in performance from prolonged starvation. Avoiding bus agent starvation is particularly important when trying to preserve the quality of real time data capture or display.
Accordingly, bus agents are typically equipped with buffering capabilities sufficient for expected worst case access latencies. This buffering becomes expensive when high bandwidth data streams such as video signals are involved. In fact, such buffers and their associated control circuitry may constitute a large portion of a video processing chip. Buffering circuits are thus an expensive necessity, the adequacy of which depends on access latencies expected on the shared bus.
Prior art arbitration techniques typically make bus allocation decisions based on the state of the system at the time of the request. This may be inefficient for buffering data streams having different bandwidths. Because such non-symmetric data streams fill or empty their respective buffers at different rates, the relative urgency of the need to access the bus may change. By the time bus access is granted to a first requesting data stream, a second data stream may have already exhausted its buffering capability even though the first requester still has available buffers. Prior art techniques fail to take advantage of an additional optimization opportunity which could allow a reduction in the amount of buffering necessary.
In particular, some prior art systems simply grant bus access to requesting agents in the order they are received. Other prior art systems permanently ascribe different priority levels to different request signals. For example, one prior art technique uses prioritized requests such as hold or address hold signals to obtain access to the bus. In such a system one device may receive higher priority access than another; however, this priority is determined either by the particular device at the time the request is made or by the designer when the system is configured. None of these systems can advantageously use the bus access latency to re-evaluate prioritization.
The same type of arbitration inefficiency also occurs where a single bus agent has one bus access mechanism, yet several data streams to manage. If the data streams arrive in unison and have the same bandwidth (i.e. they are symmetric), intelligent arbitration may not be necessary. On the other hand, where non-symmetric channels compete for bus access, prior art arbitration may not provide an optimal solution. The prior art practice of determining access priority when the request is made may necessitate larger buffers than would more optimal arbitration.
Thus, prior art arbitration techniques do not adequately consider data stream bandwidths and bus access latencies in determining access prioritization. As a result, buffering circuitry must be able to sustain operation of bus agents for latencies which are longer than may be present if a more optimal arbitration technique is used.